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At Ericsson, you can be a game changer! Because working here isn’t just a deal. It’s a big deal. This means that you get to leverage our 140+ years of experience and the expertise of more than 95,000 diverse colleagues worldwide. As part of our team, you will help solve some of society´s most complicated challenges, enabling you to be ‘the person that did that.’ We’ve never had a greater opportunity to drive change; setting the bar for technology to be inclusive and accessible; empowering an intelligent, sustainable, and connected world.

Are you in?

Backend Engineers

Job Description

Date: May 13, 2020

We are now looking for Backend engineers to join Digital ASIC & FPGA in Stockholm


Do you want to develop advanced electronics for the leading-edge mobile telecommunication systems? And be involved in making 5G happen?


Our department ASIC/FPGA Design in Kista are responsible for Digital ASIC/FPGA development for all existing and future mobile standards including 5G. This is done in close cooperation with internal and external stake holders such as standardization teams and market leading vendors. We are working with state-of-the-art technologies, tools and methodologies from our vendors. 


We are looking for several experienced, creative and innovative engineers to join our world class team. You will be part of a dynamic department where there will be opportunities for learning, trying out new roles and responsibilities and much more.

As a part of our ASIC Top Level Integration and Backend Team you will participate in the integration of our state-of-art digital ASIC´s, that are part of Ericsson´s mobile network infrastructure products for the coming 5G networks.

Responsibilities & Tasks
•    Work in a team which do timing constraints, logic synthesis, floor planning and logic equivalence checking on complex Soc ASICs. All team members are supposed to work on all tasks.
•    Focus area will be timing constraints and timing closure.
•    Responsible for full chip and block level timing constraints and timing closure on large SOC designs.
•    Work closely with and support ASIC design teams regarding timing issues in SoC block and top-level.
•    Work closely with our Silicon and IP vendors regarding timing constraints and timing closure.
•    Developing and maintaining STA and Synthesis methodology and flows. 

Key Qualifications
•    BSc or MSc level in Electrical Engineering, Computer Science, or equivalent education.
•    Strong background in ASIC design timing closure flow and methodology.
•    3+ years’ hands on experience in ASIC timing constraints generation and timing closure. 
•    3+ years’ experience in Primetime STA tool
•    2+ + years’ hands on experience in synthesis (DesignCompiler) and logic equivalence checking
•    Experience from UNIX/Linux
•    Communication and presentation skills in English are essential.
•    Quality-consciousness.
•    Travels may be needed but not required on a frequent basis.

Personal qualifications
You are driven, result oriented and able to propose improvements to existing systems, methods, and workflows. You have the ability to lead teams as well as work independently or as a team member. Communication, collaboration, and knowledge sharing is natural for you as well as a structural way of working.


Application process: 
Welcome to apply with resume in English. Last day to apply: 27th of May. 

If you have any further questions contact senior recruiter Nina Juthage at  

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Primary country and city: Sweden (SE) || || Stockholm || R&D

Req ID: 383786