At Ericsson, you can be a game changer! Because working here isn’t just a deal. It’s a big deal. This means that you get to leverage our 140+ years of experience and the expertise of more than 95,000 diverse colleagues worldwide. As part of our team, you will help solve some of society´s most complicated challenges, enabling you to be ‘the person that did that.’ We’ve never had a greater opportunity to drive change; setting the bar for technology to be inclusive and accessible; empowering an intelligent, sustainable, and connected world.

Are you in?

Master Thesis: Slice-aware Key-Value Store

Job Description

Date: Oct 19, 2019

Do you want to do your thesis with us in Kista? 


Come and start your professional journey at Ericsson. 


Would you like to take the chance to work in one of the world’s leading technology companies? We are on a quest to enable communication for everyone and everything and we do that by being driven by innovation. If you want to help us to be even more innovative - You are on the right track! 

Become a part of a truly global company working across borders in 180 countries, offering a diverse, performance-driven culture & an innovative & engaging environment where employees enhance their potential every day. Learn and grow within Ericsson, to reach your career goals. 


Are you driven by innovation? At Ericsson, we apply our innovation to market-based solutions that empower people & society to help shape a more sustainable world. 




In-memory Key-Value Store (KVS) is a type of database in which values corresponding to different keys are stored in main memory, i.e., Dynamic random-access memory (DRAM). The performance of a KVS is highly dependent on memory access times. Hence, optimizing the memory operations of a KVS would potentially improve its overall performance.

On the other hand, Intel's micro-architecture, from Sandy Bridge and forward, re-designed the Last Level Cache (LLC) by dividing it into multiple slices. Intel uses complex addressing to map different portion of the main memory to different LLC slices. Furthermore, the experiments show that one CPU core experiences different access times to different LLC slices. This characteristic motivates the slice-aware memory management scheme wherein selected portions of the DRAM will be given to an application based on this knowledge to improve the application performance.


Project Goals

The goal of this master thesis is sincerely investigating the potential improvements which can be achieved by an in-memory KVS that utilizes slice-aware memory management scheme. As part of this work, it is expected that the proper evaluation will be made by implementing a slice-aware KVS prototype which allocates the memory from the portion(s) of DRAM that is mapped to the appropriate LLC slice(s) for the CPU core that is responsible for serving the requests.


Work Description

  • The thesis work consists of several items:
  • Investigate and understand the Intel complex addressing.
  • Understand and identify the challenges of slice-aware memory management scheme.
  • Design a slice-aware KVS and identify the potential pros & cons of the solution(s).
  • Implement a prototype of slice-aware KVS based on the most promising solution(s).
  • Thoroughly analyze and evaluate the proposed solution(s). 
  • Write a proper documentation for the solution(s) and their evaluation(s).


Qualifications and Experience

  • M.Sc. Student in Computer Science/Engineering or other related fields.
  • Being familiar with memory management concepts in Linux (e.g., huge pages, physical/ virtual addresses, etc.)
  • Being familiar with programming environment in Linux.
  • Good programing skills are required (C/C++, Bash, and R).
  • Good knowledge of computer architecture is a plus. 
  • Being familiar with the architecture of a KVS is a plus.
  • Being familiar with DPDK and userspace packet processing is a plus.


Additional Details

The work is expected to start in January/February 2020. The work is proposed for one student and a duration of six months. Location is at Ericsson Research in Stockholm (Kista), Sweden.

Please submit your application in English as soon as possible - we will continuously process the applications.


Are you in?  

Then send in your application (CV, current grades and A short cover letter describing why you are interested in this master thesis) written in English and collected into one document as soon as possible.  

The application deadline is 15th November. The process will be ongoing and we will let you know as soon as we can if you move forward. Any questions? Please email Recruitment Specialist, Sylwia Kwiecień at


Ericsson provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, sexual orientation, marital status, pregnancy, parental status, national origin, ethnic background, age, disability, political opinion, social status, veteran status, union membership or genetics.

Ericsson complies with applicable country, state and all local laws governing nondiscrimination in employment in every location across the world in which the company has facilities. In addition, Ericsson supports the UN Guiding Principles for Business and Human Rights and the United Nations Global Compact.

This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, training and development.

Ericsson expressly prohibits any form of workplace harassment based on race, color, religion, sex, sexual orientation, marital status, pregnancy, parental status, national origin, ethnic background, age, disability, political opinion, social status, veteran status, union membership or genetic information.


Primary country and city: Sweden (SE) || || Stockholm || Stud&YP

Req ID: 303178