Senior Radio Clock Generation Developer
We are looking for an experienced analog circuit designer with clock signal competence that wants to move from circuit design to strategic technical leadership.
Your primary role will be to align our clock signal development activities at the Ericsson design centers in Sweden, China and Canada. You will also have close contact with external chipset suppliers to assure that technology development is in sync with Eriksson’s future needs.
Your role will include activities such as: requirement analysis, architecture design, simulations and product documentation as well as interacting with hardware and software design, integration, verification, tools design, and product lifecycle management.
• You will drive strategic technical leadership
• Perform continuous analysis and requirement handling.
• Perform trouble shooting
• Drive continuous improvements of products and processes
• Develop competence in technical domain
• B.Sc. or M. Sc. In Electrical Engineering or similar
• Radio Clock Designer with more than 8 years of experience in digital, ADC/DAC and mixer conversion clocks.
• Product development knowledge and Product Lifecycle Management knowledge
• A good understanding & knowledge of Telecommunications Networks
• Have an interest to constantly learn, communicate, interact, share information, and are willing to help others. Between organizations, internally and externally outside Ericsson
• Ability to work in teams with minimal supervision but also ability to take initiative and work independently when needed
• A quality mindset, ability for strategic thinking and a drive to always improve
• Open minded and analytical, problem-solving skills
• Keep commitments and deliver results
• You have sense of ownership, are analytical, structural and result oriented
• You are innovative and will find creative solutions when lacking information
• You have social skills and can act with confidence in for example supplier meetings
Additional Knowledge and Requirements:
• PLL modeling, being able to model cascade PLL chains with OCXO, TCXO, VCO etc.
• Making tradeoffs with different resonators, PLLs and loop bandwidths.
• Analog and digital PLL topologies from mHz to MHz loop bandwidth.
• Time stamping algorithms such as PTP and the associated performance requirements on the clock generation.
• Understanding of PLL topologies such as integer and fractional and its tradeoffs on phase noise and imperfections such as spurious effects.
• You understand electrical performance and limitations such as tradeoff between power consumption and noise performance, and the limitations of on die integrated solutions versus discrete built.
• Knowledge on time domain view of phase noise is a plus, such as Allan Deviation.
• Signal integrity for routing clocks and sync signals on PCB.
• Different signal standards for clock distribution, LVDS, LVPECL etc.
• Instrument knowledge. Spectrum analyzer, high speed oscilloscope, phase noise analyzer and network analyzer for validation, verification and trouble shooting.
• Understanding of phase noise effect on radio modulation parameters for uplink and downlink radio standards is a plus.
• Modularity thinking and worked with modular design
Last date for application: 31st August 2019
Location: Kista, Stockholm
For queries related to the position please contact the Senior Recruiter Valentyna Ivanova at firstname.lastname@example.org