Senior Architect, CPU Subsystem
Ericsson is pleased to announce the opening of a brand new design/development center in the heart of Austin, Texas. Taking advantage of the large pool of semiconductor and software talent of Austin, Ericsson is creating a new semiconductor development team here to work on 5G! We’re looking to staff a large number of design positions across the entirety of a semiconductor development program.
Do you want to develop advanced silicon, software, systems, and models for the leading edge mobile telecommunication systems? And be involved in making 5G happen? Want to be a part of a brand new design center?
The ASIC Design department at Ericsson is responsible for Digital ASIC and SoC development for all existing and future mobile standards, including 5G. The development is done in close cooperation with internal and external stake holders such as standardization teams and market leading silicon vendors and ASIC Design houses. We are working with state of the art SI-technologies, EDA tools and methodologies.
We are looking for experienced system architects that can drive systemization of our Digital ASIC & FPGAs in our Austin-based team.
As part of our Digital ASIC & FPGA SoC team, you will drive and contribute to the definition, systemization, and development of our digital ASICs and FPGAs, that are part of Ericsson´s mobile network infrastructure products for the coming 5G network.
You will be actively involved from the early pre-study phase through definition and development of the ASIC/FPGA project until the product has been released. The work is done in close collaboration with colleagues in other sites.
As a system architect, your primary responsibility will be on SOC architecture with significant overlap with system and platform architecture.
Specific responsibilities include, but are not limited to:
- Definition and optimization of SoC and/or CPU subsystem performance, power and cost metrics, in conjunction with product planning, system and software architecture teams
- Definition of key IP features, requirements, and selection criteria
- Establishment of SoC level performance and power modeling and analysis methodologies and infrastructure
- Active participation in SoC floorplan, key implementation tradeoff analysis, package selection and design
- Interface with software developers, partners and customers to assist in system bring-up and deployment
- Participate in development of system validation plans
- ASIC, SoC or FPGA design experience at IP, CPU/Memory sub-system and/or chip level
- Proven ability to architect and develop ARM and/or x86 CPU subsystem
- Proven experience with performance/power/area tradeoffs and optimization
- Proven skills in Logic design and Microarchitecture
- Debug experience at IP, sub-system, full chip level
- Static timing analysis experience
- Integration experience
- Multi/Many Core CPU Architecture knowledge and experience
- High speed interface protocols experience
- Silicon debug
- Technical leadership experience, leading and mentoring other engineers
- Self-starter, works well with ambiguity
- Masters in Electrical, Computer engineering, 10+ years of experience
You are driven, result oriented and able to propose improvements to existing systems, methods, and work flows. You can also coach and mentor younger colleagues. You have the ability to lead teams as well as work independently, or as a team member. Communication, collaboration, and knowledge sharing is natural for you as well as integral way of working.
DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees assigned to this classification. They are not intended to be construed as an exhaustive list of all responsibilities, duties and skills required of employees assigned to this position. Therefore employees assigned may be required to perform additional job tasks required by the manager.
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Primary country and city: United States (US) || || Austin || R&D
Req ID: 219586