Senior ASIC RTL Designer
Ericsson is looking to staff several design positions at its new design/development center in the heart of Austin, Texas. Taking advantage of the large pool of semiconductor and software talent of Austin, Ericsson is building a new semiconductor development team here to work on 5G!
Do you want to develop advanced silicon, software, systems, and models for the leading edge mobile telecommunication systems? And be involved in making 5G happen? Want to be a part of a brand new design center?
The ASIC Design department at Ericsson is responsible for Digital ASIC and SoC development for all existing and future mobile standards, including 5G. The development is done in close cooperation with internal and external stake holders such as standardization teams and market leading silicon vendors and ASIC Design houses. We are working with state of the art SI-technologies, EDA tools and methodologies.
We are looking for several Experienced, Creative and Innovative engineers to join our world class team. You will have a unique opportunity to work and gain competence in several areas such as modeling (TLM), RTL-design, verification, systemization, integration, synthesis, timing and SW development. You will be part of a dynamic team where there will be opportunities for learning, trying out new roles and responsibilities and much more.
You have a great interest in learning new things every day and want to make a difference. You have a very positive attitude and thrive on new challenges. You are keen to solve problems and do so creatively. Where there is change you see opportunities. You are a strong team player and a very communicative person, but you also work well independently. You make sure to reach results with high quality and on time.
· ASIC, SoC or FPGA design experience at IP, sub-system and/or chip level
· Proven skills in Logic design and Microarchitecture
· Debug experience at IP, sub-system, full chip level
· Static timing analysis experience
· Integration experience
· Multi/Many Core CPU Architecture knowledge and experience
· Silicon debug
· System Verilog/Verilog/VHDL
· Technical leadership experience
· ARM CPU subsystem experience
· Master of Science in Electrical Engineering, Computer Engineering or equivalent experience.
DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees assigned to this classification. They are not intended to be construed as an exhaustive list of all responsibilities, duties and skills required of employees assigned to this position. Therefore employees assigned may be required to perform additional job tasks required by the manager.
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Primary country and city: United States (US) || || Austin || IT; R&D
Req ID: 216766