Ericsson Lund | Master Thesis - Age Monitoring in FPGAs

Posted date: Nov 18, 2020

Location: Lund, M, SE

Company: Ericsson

Thesis Background

Semiconductor devices are susceptible to different degradation mechanisms that cause the affected devices to not be operable within their original specifications (or become completely unusable). The degradation process is referred to as ageing. For example, the Negative Bias Temperature Instability causes the threshold voltage of the P-type metal-oxide-semiconductor (PMOS) transistors to increase, which results in reduction of the frequency at which the affected circuit can be clocked.


In the older technology nodes, ageing effects were either insignificant (compared to the expected useful life of devices) or were avoided by allotting enough margins during the design. As semiconductor technology progresses towards smaller feature sizes, however, the ageing effects become more pronounced on the one hand and design margins shrink (due to increased variation) on the other hand. Therefore, designing with the margins considered for the worst case might not be a viable solution for the future generation of semiconductor devices. A workaround is to add monitoring circuitry inside the devices and track the state of the ageing, thus enabling accurate estimation of the remaining useful life and preventive maintenance when needed.


Field-programmable gate array (FPGAs) are typically in the forefront of adopting new semiconductor technology generations. Therefore, it becomes important to consider using ageing monitoring in FPGA-based designs for future product generations.


Project Goals

A first vital step in this thesis work will be a research of existing literature on ageing in FPGAs and proposed monitoring techniques. The research should cover the following

  • Investigate which degradation mechanisms have been found to be more relevant/dominant for FPGA fabrics and if (and how) that landscape will change for the modern and next generation FPGAs
  • Investigate and compare which monitoring circuitry and methods have been proposed, which degradation mechanisms they target, and how they compare in terms of area, resources, accuracy, etc. Carrying out the comparison might require implementation of some of the proposed monitoring schemes (either due to the information missing in the original publication or due to fairness in comparison).


The second step will be the deployment of the implemented monitoring circuitry in FPGAs of the same generation but with different usage background and see if the monitors are capable of detecting ageing in the selected FPGAs.



Final year student commencing thesis work Spring 2021 in System on Chip, Electronics Design Engineering, Electrical Engineering or similar.


Familiarity (preferably via courses) with all the following three areas:

  • VLSI design concepts
  • Hardware description languages
  • FPGAs and associated technology


Also, a good knowledge of programming and scripting languages is a plus.



Please compile your Cover Letter, CV and Grade Transcripts in to one PDF and apply!

Interviews will be ongoing!

Credits: 30 HP/student

Students: 2

Location: Lund

Recruiter: Richard Tjong richard.tjong@ericsson.com

Hiring Manager: Mikael Lostedt Manager Chipset & Software Technology

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